The other comment already covered why comparing CAS latency is misleading. CAS latency is measured in clock cycles. Multiply by the length of a clock cycle to get the CAS delay.
So? If the net result is more reliable memory, it doesn't matter.
Many things in electrical engineering use ECC on top of less reliable processes to produce a net result that is more reliable on the whole. Everything from hard drives to wireless communication. It's normal.
Just like increasing the structure size "only" decreases the likelihood of bit flips. Correcting physical unreliability with more logic may feel flimsy, but in the end, probabilities are probabilities.
DDR5 is more reliable. Where are you getting this info that DDR3 lasts longer?
DDR5 runs at lower voltages, uses modern processes, and has on-die ECC.
This is already showing up in reduced failure rates for DDR5 fleets: https://ieeexplore.ieee.org/document/11068349
The other comment already covered why comparing CAS latency is misleading. CAS latency is measured in clock cycles. Multiply by the length of a clock cycle to get the CAS delay.