This is actually surprisingly hard to do reliably when you're not using an FPGA but a large board with TTL or CMOS logic. I really struggled with keeping outputs 'muted' until the control system was up and running in one particular design. In the end my solution was to have a single relay in the supply line to the power electronics and to only trigger this relay after the control system output a complex code on it's IO lines. The chances of this happening randomly during the power on sequence were nil and once the system was powered up it did not matter any more (relay held itself and the only way to reset it was an emergency stop after which the whole machine would be cycled anyway).

Hackish but it worked very well.

The root cause of the complexity was that the system contained way too many circuits that could be powered up/down independently, some of those under end user control and that there was no easy way for me to reliably sequence power so the only place where any difference could be made was the end stage ignoring everything in between.

Connected to the end stage were some pretty powerful servos and inputs to inverters driving large AC motors so keeping things 'off' until the time was right was rather crucial to the safe operation of the machinery.

As far as I know these systems never failed to reliably power up in production even with 1000's of systems sold and used by three shifts daily.