And which cores currently support it? And unless the answer is “all”, it will not be used. Feature detection works for well-isolated high-performance kernels using things like AVX. No one‘s going to do feature detection for load/store instructions. Which means that all your binaries will be compiled to the lowest common denominator
As I said, it's mandatory in RVA23 profile. In fact it has been mandatory since RVA22 profile. A bunch of cores appear to support RVA22.
Whether prebuilt distribution binaries support it or not, I can't tell. Simple glance at Debian and Fedora wiki pages doesn't reveal what profile they target, and I CBA to boot an image in qemu to check. In the worst case they target only GC so they won't have Zba. Source distributions like Gentoo would not have a problem.
In any case, talking about the current level of extension support is moving the goalposts. You countered "there is nothing about the RISC-V architecture which inherently prevents it from ever being competitive with ARM" with "Lack of reg+shifted reg addressing mode", which is an argument about ISA, not implementation.
ubuntu announced they want to suppory RVA23 in their next LTS 25.04 IIRC. That doesn't really make sense, unless we get new hardware with RVA23 support till then.
Zb extension is in both RVA22 and RVA23 profiles, meaning application cores (targeting consumer devices like smartphones) designed in the past few years almost certainly have shXadd instructions in order to be compatible with the mainstream software ecosystem
You are aware that hardware takes time to build, tapeout and productise?
On the open-source front, I can right now download a RVA23 supporting RISC-V implementation, simulate the RTL and have it out perform my current Zen1 desktop per cycle in scalar code: https://news.ycombinator.com/item?id=41331786 (see the XiangShanV3 numbers)
RISC-V has existed for over a decade and in that time no one has got close to building a competitive non microcontroller level CPU with it.
How long is this supposed to take?
How long until it is accepted that RISC-V looks like a semiconductor nerd snipe of epic proportion designed to divert energy away from anything that might actually work? If it was not designed for this it is definitely what it has achieved.
The name RVA23 might give you a hint around which time the extensions required for high performance implementations to be viable were rougly standardized.
The absolutely essential bitmanip and vector extensions were just ratified at the end of 2021 and the also quite important vector crypto just in 2023.
So it took 10 years to ratify absolutely essential extensions?
Somehow I suspect in 10 years there will be a new set of extensions promising to solve all your woes.
Seriously, the way to do this is for someone to just go off and do what it takes to build a good CPU and for the ISA it uses to become the standard. Trying to do this the other way around is asking for trouble, unless sitting in committees for twenty years is actually the whole idea.
> So it took 10 years to ratify absolutely essential extensions?
Essential for what? RISC-V was not just created for high performance of application cores.
The first couple years RISC-V was mostly for university research work.
Turning it into a fully capable alternative only started later and yes, that takes a number of years.
> Somehow I suspect in 10 years there will be a new set of extensions promising to solve all your woes.
Its about delivering the same as Intel/ARM and they have that now. Yes, in 10 years more extentions will exist, this is true for RISC-V and ARM and x86.
> Seriously, the way to do this is for someone to just go off and do what it takes to build a good CPU and for the ISA
No it doesn't happen that way because the company wouldn't do that wouldn't open source their ISA design. Or at least not historically.
So a different path was taken to create and open standard and it worked out pretty well, even if it doesn't do what your imagination wants.
Everything needed for high performance was ratified in 2021, just two years after the base spec.
That's RVA22 and Vector 1.0.
Low-end hardware implementing the spec already exists (Milk-V Jupiter). High end implementations (e.g. Ventana Veyron V2, designed for servers) will be deployed in 2025.
> Everything needed for high performance was ratified in 2021
Assuming you are right, getting on for four years after even this we would have a high performance implementation of it to look at which proves that it really is everything needed . . .
To re-iterate: you have no basis for saying it is high performance because it has not been shown to be so.
When a track record has been established _then_ claims of this kind can be made, but not before.
I have worked with chip makers at both ends (I was doing games which they used for testing, but they also tried to get our input for what their next designs should do) and honestly learned that these people are absolute dreamers. This was not helped by the nearly constant regularity with which we found performance destroying design flaws. Some prototypes were aborted as a result (dramatic overheating is quite a problem) but most products launched to go nowhere since they were now unspectacular.
The dreaming is necessary to enable them to get up and try again, but it means you should not believe a word they say until it works.
Realistically, there's no way every company that has high performance microarchitectures available for licensing is lying, and that the clients it already licensed the IP to are covering for them.
It is also unreasonable to think that each and every industry veteran who has designed successful, competitive high performance microarchitectures in the past and is now working on RISC-V IP is for some reason suddenly unable to deliver.
Waiting will give you confirmation, in the form of seeing your competitor's successful products in the market, but at the cost of missing your own chance.
